From:    Bill McEwen bill@amiga.com
Subject: VP "Omissions" and problems re SDK...
Date:    Fri, 7 Jul 2000 10:08:01 -0700

Answer to this posting from John Wiederhirn on comp.sys.amiga.misc

Regarding message from J.F. Wiederhirn,

There are some valid points, but you overemphasise the points significantly.
The extent to which you dismiss the platform is at odds with the reality of
the graphics and Java performance [for example].

> >> >1.  Efficient register usage...or the lack thereof.
> >> >
> >> >VP code allows (hell, suggests) you to registers whenever possible.
> >> >They scope registers at subroutine limits (among others, the details
> >> >aren't really relevent to the problem).
> >> >
> >> >The problem is that you cannot direct register usage, or even
> >> >prioritize it.  You can scope it slightly, by indicating when a
> >> >register is last-used.  Every register usage is in the end evaluated
> >> >by the translator and handled based on it's algorithms. Since (and
> >> >I'll avoid the extensive mathematical proofs involved) their optimizer
> >> >cannot understand more than basic algorithms, that means it is very
> >> >difficult to do tight register-based optimization on code.

You cannot direct register usage, just as you can't in C. So really you are
saying that you cannot write as efficient code in VP as you can by
hand-crafting native assembler. This is undeniably true and nobody pretended
otherwise. VP does give you, however, a means of writing low-level code,
sacrificing the minimum of efficiency possible with a portable solution. For
ultimate performance, certain operations would need to be written in native
but when you don't do this, you still get near-optimal performance in a
portable manner.

> >> >2.  MMX, SSE, maybe someday?
> >> >
> >> >The reason for the vague answers regarding how MMX and SSE were to be
> >> >supported is now very clear to me.  They aren't supported from a
> >> >programmer standpoint as far as I can discern.  Even the documentation
> >> >for the PII interfaces leaves it unclear whether platform-specific
> >> >code (more on that in a bit) can safely use those instructions, since
> >> >there's no documentation as to whether those registers are state-saved
> >> >in the current SDK.

As it happens, they are saved.

The CPU documentation details which native registers are used by the VP
environment. Development of PII tools such as the first level interrupt
handler is directly based on that information. For example,
sys/cii/arm6/cpu.html gives the information about native register usage for
anyone wishing to write an ARM PII.

> >> >The VP in the SDK does not appear to support any mechanism for issuing
> >> >MMX or SSE instructions.

To get ultimate performance you would need to abstract at a library level
and develop native MMX-based implementations. So MMX type instructions can
be used now. They have not been abstracted into VP as there is no
sufficiently common model across all processors with MMX-type operations to
get any degree of efficiency. However, as noted in this paragraph already,
an application that can make good use of these instructions on a particular
processor can contain some native tools containing the MMX type instructions
for that particular processor. These tools can be macro-ised and embedded to
get code that looks and behaves like the MMX instructions were fully
supported.

Would you suggest an abstraction that could be used? You obviously have some
good ideas in mind for you to have made such comments.

> >> >3.  Cache?  Hello?
> >> >
> >> >This omission appears to be the second-most glaring to me, from a
> >> >low-level perspective.  VP code has neither any concept of cache, nor
> >> >any way to actually control it.  While that makes some sense from a
> >> >software interpreter/compiler standpoint, it totally ignores that
> >> >under the VP there is a real CPU with real cache.  The idea that
> >> >meaningful driver code can be written is VP code is laughable given
> >> >that the VP has no way to actually handle cacheable vs non-cacheable
> >> >contents.

Cache? Hi!

This is not a VP issue at all. Do any processors have native instruction
modifiers that allow cache usage to be modified on a per instruction basis?
I do not know of any. I would have thought that most of this work will be by
programming a CPU register(s) to control the cache usage (i.e. coarse: turn
off at start - turn on at end for all memory operations on a memory bank.
fine: declare a pointer type to be uncached so that any use of that pointer
is not cached.). Note that in your question 4 there is a reference to
declaring a memory area as cached or not cached, so that is the level of
cache management expected. So, that is clearly not a VP issue. In fact,
intent is uniquely placed to take advantage of an architecture where cache
lines are controlled by individual flags within the pointer. The trouble is,
again, there is no good abstraction for this concept. It is up to individual
platforms and drivers to have these concepts defined and used if required.
And this is all perfectly possible on intent. An example might be that two
memory objects are declared, one returns cached memory, one not cached.
These can even allocate from the same underlying pool, although you are
likely to find that the cache is turned off and on at larger boundaries than
the byte.

The kernel and tool loaders are cache aware in that they call
sys/cii/flushicache during tool loading and code relocation to allow a
platform to clean/flush caches if required. Although this is a CII tool, it
is actually implemented in the PII since cache details may differ on
platforms with apparently similar cores. The tool is directly accessible to
device drivers if developers wish to use it. Where DMA and cache interaction
is an issue, the PII implementer would write tools for the device driver
writer to use to e.g. clean/writeback a DCache.

The whole point of the PII is that there is a fixed set of tools required by
the OS on all platforms plus a "platform specific" optional set that need to
be written to address specific issues on the target platform. This maintains
the portability and encapsulates the "dirty stuff" in one layer. PIIs have
successfully been implemented on many platforms with caches and "take
advantage" of the cache just like any software.


> >> >4.  Memory-space attributes.
> >> >
> >> >I don't even know where to start with this.  The PII mechanisms
> >> >offered, as far as I could discern (and the documentation on this is
> >> >far from centralized) appeared to support the following ops:  You can
> >> >map physical memory to Amiga memory, and unmap it.  You can obtain the
> >> >physical address of mapped memory.  You can do a couple other usual
> >> >mapping tricks with that memory.
> >> >
> >> >You CANNOT set any attributes for the memory range in question, such
> >> >as cached/non-cached, write-combined/non-write-combined, etc.  Who the
> >> >hell's brain-fart was responsible for that?  Jeez, Tao's been tooling
> >> >on this thing for years and years, and they never once thought being
> >> >able to set stuff as non-cached was valuable?

The cacheing issue has already been covered. Any other attributes fall into
the same category. Have you come across write-combined/non-write-combined?
Even if these exist, it wouldn't really change anything. If a need is
identified, functions can easily be added to the PII. It has been
constructed to be extensible.

The primary focus for intent has been on embedded systems where the MMU is
used to set up a fairly simple memory space with mostly 1:1 translation from
physical to virtual space. These mappings are set up at boot time. The
mapping tools you refer to were developed several years ago for the DOS
platform and are not used on any other platform.

> >> >5.  Cross-platform.  Well, kinda.
> >> >
> >> >The docs themselves suggest that tools (think of em as DLLs, they work
> >> >almost exactly the same as Windows DLLs) can hold multiple versions of
> >> >the same code for different environments.  In fact, they specifically
> >> >mention that optimized versions of code for a given environment can be
> >> >included in a tool, as well as a generalized VP version.
> >> >
> >> >So much for platform neutrality and cross-platform compatibility.
> >> >Their solution is no different than JNI, and suffers precisely the
> >> >same issues.

This isn't true. JNI is not portably defined across platforms.
I don't see really what the complaint is here.

> >> >6.  Interrupts
> >> >
> >> >I saved this for last because, well, "the horror, the horror...".  As
> >> >I've already mentioned under VP your cache control is non-existent.
> >> >To the issue of interrupt handling, well, I can only pass along the
> >> >trauma and suggest anyone really interested buy the SDK.  You'll be
> >> >impressed to see the mechanism documented on paper, if ya don't tear
> >> >out your own eyeballs.

I expect here you are commenting on the efficiency of the interrupt handing
model. Not altogether a surprise, if someone's obsessed by these issues.

There is nothing wrong with the interrupt model for 'normal' usage
platforms. Those who are obsessed are at liberty to fit in their own
architecture here. Platforms with little hardware support for devices may
also need to do the same thing to be able to service interrupts at a very
low patency. The intent model does not precluse this at all.

> >> >On a personal note, I just got stuck in a wheelchair after a spinal
> >> >injury.  I _really_ wanted this to turn out as a review of cool
> >> >technology because my mood was already dour.  I'm left after viewing
> >> >the technology wondering what the hell Tao's been doing for the last
> >> >few years, and why Amiga thought this technology was
> >> >desktop-appropriate.  The VP, while totally appropriate for embedded
> >> >and handheld concerns, isn't remotely appropriate for high-bandwidth
> >> >desktop concerns.

Some things are undeniably true, nonetheless. The 2D graphics functionality
and performance is unparalleled. This is all done in VP. It shows that using
this technology it is possible to develop highly performing portable
software (near optimal, not completely optimal on all architectures). The
JVM and libraries are still be best available. It is true that the
superiority of the technology is greatest in embedded space but to suggest
that it is worthless is not realistic.

Finally, it is worth pointing out that it is impossible to refute bland
allegations that do not give any substance.